Panel: New Research Problems in the Emerging Test Technology

Problem 1: How high level design can cope up with realistic low level fault hypotheses? The development of manufacturing possibilities leads to an ever increasing number of devices put on a circuit. To cope up with the complexity, the designer must work at higher and higher levels. But, faults actually occur at the layout (transistor) level. This leads to a large number of fault hypotheses. The main problem is that there remains a gap between the R&D steps in design and R&D steps in testing.